Include all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
Should be able to interface with Front End Design team to resolve Design Issues
- Must possess 3-7 years of hands on experience, P&R from RTL to GDS including timing closure and Physical verification.
- Design experience in all aspects of physical design.
- Proficient and powerful user of Synopsys Tool Suite (DC/ICC/Star/PT).
- Technologies: 28nm and below.
- Experience in Mentor Calibre tools to run Physical verification
- Experience in Cadence Voltus to run IR-analysis is a Plus.
- Experience in Tcl/Tk, PERL, Makefile is a Plus
- Excellent verbal and written communication skill is required.
- Excellent interpersonal and analytical skills with an ability to work independently and within a team is required.
- Highly motivated, excellent team player, and customer oriented.
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