Looking for Test engineer with proficiency in VHDL/verilog coding, test bench setup, test case creation and verificaion.
- Experience in Design for Test (DFT) of large, lower geometry SOC designs.
- Experience in DFT concepts, test mode.
- Good knowledge in Boundary Scan, ATPG Scan, and memory testing.
- Proficiency in VHDL/Verilog coding, test bench setup, test case creation and verification
- Proficiency in mixed signal IP verification such PCIe Phy, PLL etc
- Experience with industry standard tools for DFT and Verification (Synopsys, Cadence)
- Proficiency high level programming and scripting languages such as “C”, “C++”, Perl
- Knowledge or Experience in Test development and Product engineering will be an added advantages
- if u find this opening relevant,kindly send your resume to firstname.lastname@example.org